December 16, 2014, IEDM, San Francisco—Ken Chang from Xilinx described their efforts in designing and characterizing analog sub-functions in advanced node CMOS technologies. The high device parametric variability of active and passive devices requires specialized design techniques for stable, high-performance circuits.
The increasing speeds for data transmission is affecting storage, and computer architectures. Scaling process technologies have helped to reduce the energy per bit due to the predominance of digital circuitry in the wireline transceivers. The challenge is that the data speed is dominated by the analog clocking and equalization circuits, which don't track process changes well.
The device parameter sensitivities are shown in designs in a 20nm planar and 16nm FinFET processes. With proper design techniques, the transceiver in 20nm operates up to 16.3Gb/s and achieves measured bit error rate lower than 10-15 over 28dB channels. The clock generation architecture for a quad transceiver in a 20nm FPGAuses LC PLLs to provide high-precision, low-jitter clocks. Three LC VCOs are used to cover a 2:1 frequency range to avoid any operating frequency gap. Two LC PLLs are used to offer two independent frequencies per quad transceiver. For lower line rates (< 6Gb/s), the ring PLL which provides a much wider operating range is used per channel.
The frequency adjustment circuits of each LC VCO utilize varactors and switched metal capacitors. We compared capacitance versus voltage (CV) for the planar
and FinFet accumulation mode NMOS varactors. The desired CV curve for low jitter PLL applications should provide a large linear range to maintain constant and moderately small CV gain over the full control voltage (Vcnt). Higher CV gain translates to higher VCO gain and higher jitter in the LC VCO. In a FinFet process, Vt shift pushes the CV curve to higher voltages and sharper slope, resulting in a higher CV gain. Both processes have challenges in the pJ/bit/dB to accomplish wide range, low jitter LC PLL design.
For a DC coupled NMOS LC VCO, the voltage across the varactor is defined by Vgg=Voutp/n-Vcnt. Higher threshold translates into lower tuning range for the varactor An alternative is to AC couple the varactor and set the bias voltage in the center to achieve higher tuning range. However, AC coupling capacitors are large and limit the tuning range of the VCO. The challenges for large tuning range of LC VCO design are made worse due to PVT (process, voltage and temperature) sensitivity, which results in frequency drift over the operating range. A low C-V slope is desired for low-jitter VCOs. FinFet varactors show higher threshold and also have a sharper C-V curve compared to planar varactors.
The receiver includes the analog front-end, deserializer, and clock generation circuits. The analog front-end is composed of a continuous time linear equalizer (CTLE), slicers, slicer offset cancellation circuitry, and decision feedback equalizer (DFE). The receive data from analog front-end is then sent to the deserializer to parallelize the high-speed bit stream and is ultimately sent to Physical Coding Sublayer (PCS) for use by the FPGA fabric. The circuit utilizes a bipolar transistor to sense temperature in the form of voltage which is amplified and used to control another set of varactors to counter the VCO frequency shift due to voltage and temperature shift.
The phase interpolator (PI) is used to provide the clocking for clock data recovery (CDR). The transmitter is composed of the serializer, a finite impulse response filter (FIR), output transmitter driver, and the clock generation circuitry. In the transmitter, the primary analog circuit is the output driver and the phase interpolator. As process node scales and line rate increases, several challenges must be addressed in transceiver design to deal with voltage supply scaling and reduced dynamic range, higher device variability and mismatch due to small geometry, and power density.
Typical LC VCOs are segmented into several small frequency bands. Once a frequency band is selected and PLL is locked, it must work over extreme temperature and voltage variations without resetting or switching the frequency band. Temperature stability or compensation circuits are added to insure proper operation over such PVT conditions The CTLE must operate linearly for DFE to achieve highest performance. Therefore, the TiN resistor is used for its load to achieve good linearity.
Unfortunately, the variation of the TiN resistor can be as high as 20 percent. To maintain a constant transfer function over PVT, a constant Gm bias circuit is used to provide the stable gain for CTLE. In addition to PVT variations, the device mismatches in the front-end, including CTLE and slicers, can impair the receiver input sensitivity – a critical performance parameter for the wireline receiver. To combat the random variations, offset cancellation circuit is added in each slicer.
The transmitter circuitry uses a bias circuit to account for load variability. The transmitter output needs to provide a 100 Ohm differential load to avoid channel reflections. The load resistor is made of several parallel TiN resistors with PMOS switches to compensate for PVT variations. The impedance calibration employs a central replica circuit. The calibrated codes are then broadcast to every quad to operate in the linear mode for all PVT. Gm is ~ to 1/R. The overall gain is set by the ratio of two TiN resistors. The bias circuit has two stable operating points. The start-up circuit is to avoid the circuit get stuck in the all-zero state.
